1. Field of the Invention
The present invention relates to a circuit diagram drafting system and method and to a computer program product for the same, more particularly relates to a circuit diagram drafting system and method and a computer program for the same enabling easy confirmation of connections of the drafted circuit diagram.
2. Description of the Related Art
When electronic equipment is designed, the logic of the designed electronic equipment, that is, the connections among the components forming the electronic equipment, are expressed by a circuit diagram. In recent years, components of electronic equipment have been made smaller in size and have been arranged at a higher density. As a result, the drafted circuit diagrams have also become huge. The hardware or software for drafting circuit diagrams is provided with a design rule check function for verifying if there are any omissions in the connections of the drafted circuit diagrams or if there are any mistaken connections. However, in the end, a human operator has to check the connections by going through the circuit diagrams. To check circuit diagrams, the drafted drawings have been printed out on paper and the checked components or connections etc. have been colored by a marker pen etc. to verify that there are no errors or omissions in the circuit diagrams.
However, circuit design work almost never is completed at one go. Usually, the circuit design is reworked several times. Therefore, each time reworking the design, the work of verification of the circuit diagrams is necessary. The work of coloring the circuit diagrams by a marker pen is therefore performed each time the circuit diagrams are printed out. Therefore, there was the problem that an extremely large amount of time and labor were required for the above work.
The technology proposed up to now included one automatically extracting connection paths between circuit elements in a circuit diagram and highlighting the circuit elements and signal lines on the connection paths (see Japanese Patent Publication (A) No. 5-252286 and Japanese Patent Publication (A) No. 5-314200). However, since the techniques described in these publications perform processing for automatically extracting connection paths between the circuit elements, when the circuits checked were gigantic in size, there were problems in the efficiency, reliability, and flexibility of the verification work of the circuits.